Index of /shared/bigslow/tmp/trash3/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/


../
AsmParser/                                         05-Nov-2024 13:39       -
Disassembler/                                      05-Nov-2024 13:39       -
GISel/                                             05-Nov-2024 13:39       -
MCA/                                               05-Nov-2024 13:39       -
MCTargetDesc/                                      12-Oct-2025 01:53       -
TargetInfo/                                        05-Nov-2024 13:39       -
RISCV.h                                            05-Nov-2024 13:39    3504
RISCV.td                                           05-Nov-2024 13:39    2988
RISCVAsmPrinter.cpp                                05-Nov-2024 13:39     39K
RISCVCallingConv.td                                05-Nov-2024 13:39    2770
RISCVCodeGenPrepare.cpp                            05-Nov-2024 13:39    7318
RISCVCombine.td                                    05-Nov-2024 13:39     940
RISCVDeadRegisterDefinitions.cpp                   05-Nov-2024 13:39    4264
RISCVExpandAtomicPseudoInsts.cpp                   05-Nov-2024 13:39     26K
RISCVExpandPseudoInsts.cpp                         05-Nov-2024 13:39     22K
RISCVFeatures.td                                   05-Nov-2024 13:39     62K
RISCVFrameLowering.cpp                             05-Nov-2024 13:39     66K
RISCVFrameLowering.h                               05-Nov-2024 13:39    4210
RISCVGISel.td                                      05-Nov-2024 13:39    7027
RISCVGatherScatterLowering.cpp                     05-Nov-2024 13:39     20K
RISCVISelDAGToDAG.cpp                              05-Nov-2024 13:39    145K
RISCVISelDAGToDAG.h                                05-Nov-2024 13:39    9283
RISCVISelLowering.cpp                              12-Oct-2025 01:53    865K
RISCVISelLowering.h                                05-Nov-2024 13:39     45K
RISCVInsertReadWriteCSR.cpp                        05-Nov-2024 13:39    6166
RISCVInsertVSETVLI.cpp                             05-Nov-2024 13:39     64K
RISCVInsertWriteVXRM.cpp                           05-Nov-2024 13:39     14K
RISCVInstrFormats.td                               05-Nov-2024 13:39     19K
RISCVInstrFormatsC.td                              05-Nov-2024 13:39     11K
RISCVInstrFormatsV.td                              05-Nov-2024 13:39    8675
RISCVInstrGISel.td                                 05-Nov-2024 13:39    2121
RISCVInstrInfo.cpp                                 12-Oct-2025 01:53    145K
RISCVInstrInfo.h                                   05-Nov-2024 13:39     15K
RISCVInstrInfo.td                                  05-Nov-2024 13:39     83K
RISCVInstrInfoA.td                                 05-Nov-2024 13:39     20K
RISCVInstrInfoC.td                                 05-Nov-2024 13:39     41K
RISCVInstrInfoD.td                                 05-Nov-2024 13:39     28K
RISCVInstrInfoF.td                                 05-Nov-2024 13:39     34K
RISCVInstrInfoM.td                                 05-Nov-2024 13:39    5791
RISCVInstrInfoSFB.td                               05-Nov-2024 13:39     11K
RISCVInstrInfoV.td                                 05-Nov-2024 13:39     76K
RISCVInstrInfoVPseudos.td                          12-Oct-2025 01:53    317K
RISCVInstrInfoVSDPatterns.td                       05-Nov-2024 13:39     76K
RISCVInstrInfoVVLPatterns.td                       05-Nov-2024 13:39    163K
RISCVInstrInfoXCV.td                               12-Oct-2025 01:53     36K
RISCVInstrInfoXSf.td                               12-Oct-2025 01:53     36K
RISCVInstrInfoXTHead.td                            05-Nov-2024 13:39     38K
RISCVInstrInfoXVentana.td                          05-Nov-2024 13:39    2039
RISCVInstrInfoXwch.td                              05-Nov-2024 13:39    8076
RISCVInstrInfoZa.td                                05-Nov-2024 13:39     11K
RISCVInstrInfoZalasr.td                            05-Nov-2024 13:39    2342
RISCVInstrInfoZb.td                                05-Nov-2024 13:39     35K
RISCVInstrInfoZc.td                                05-Nov-2024 13:39     12K
RISCVInstrInfoZcmop.td                             05-Nov-2024 13:39     977
RISCVInstrInfoZfa.td                               05-Nov-2024 13:39     11K
RISCVInstrInfoZfbfmin.td                           05-Nov-2024 13:39    3966
RISCVInstrInfoZfh.td                               05-Nov-2024 13:39     30K
RISCVInstrInfoZicbo.td                             05-Nov-2024 13:39    3796
RISCVInstrInfoZicfiss.td                           05-Nov-2024 13:39    3045
RISCVInstrInfoZicond.td                            05-Nov-2024 13:39    2344
RISCVInstrInfoZimop.td                             05-Nov-2024 13:39    3072
RISCVInstrInfoZk.td                                05-Nov-2024 13:39    8793
RISCVInstrInfoZvfbf.td                             05-Nov-2024 13:39    1426
RISCVInstrInfoZvk.td                               05-Nov-2024 13:39     47K
RISCVMachineFunctionInfo.cpp                       05-Nov-2024 13:39    1626
RISCVMachineFunctionInfo.h                         05-Nov-2024 13:39    6194
RISCVMacroFusion.td                                05-Nov-2024 13:39    3314
RISCVMakeCompressible.cpp                          05-Nov-2024 13:39     15K
RISCVMergeBaseOffset.cpp                           05-Nov-2024 13:39     20K
RISCVMoveMerger.cpp                                05-Nov-2024 13:39    8320
RISCVOptWInstrs.cpp                                05-Nov-2024 13:39     24K
RISCVPostRAExpandPseudoInsts.cpp                   05-Nov-2024 13:39    4400
RISCVProcessors.td                                 05-Nov-2024 13:39     22K
RISCVProfiles.td                                   05-Nov-2024 13:39     10K
RISCVPushPopOptimizer.cpp                          05-Nov-2024 13:39    5768
RISCVRedundantCopyElimination.cpp                  05-Nov-2024 13:39    5873
RISCVRegisterInfo.cpp                              05-Nov-2024 13:39     35K
RISCVRegisterInfo.h                                05-Nov-2024 13:39    6005
RISCVRegisterInfo.td                               05-Nov-2024 13:39     24K
RISCVSchedRocket.td                                05-Nov-2024 13:39    9192
RISCVSchedSiFive7.td                               05-Nov-2024 13:39     59K
RISCVSchedSiFiveP400.td                            05-Nov-2024 13:39     13K
RISCVSchedSiFiveP600.td                            05-Nov-2024 13:39     49K
RISCVSchedSyntacoreSCR1.td                         05-Nov-2024 13:39    4114
RISCVSchedSyntacoreSCR3.td                         05-Nov-2024 13:39    5820
RISCVSchedXiangShanNanHu.td                        05-Nov-2024 13:39    9856
RISCVSchedule.td                                   05-Nov-2024 13:39     16K
RISCVScheduleV.td                                  05-Nov-2024 13:39     50K
RISCVScheduleXSf.td                                05-Nov-2024 13:39    2056
RISCVScheduleZb.td                                 05-Nov-2024 13:39    4791
RISCVScheduleZvk.td                                05-Nov-2024 13:39    6292
RISCVSubtarget.cpp                                 05-Nov-2024 13:39    7618
RISCVSubtarget.h                                   05-Nov-2024 13:39     11K
RISCVSystemOperands.td                             05-Nov-2024 13:39     16K
RISCVTargetMachine.cpp                             05-Nov-2024 13:39     22K
RISCVTargetMachine.h                               05-Nov-2024 13:39    2670
RISCVTargetObjectFile.cpp                          05-Nov-2024 13:39    6182
RISCVTargetObjectFile.h                            05-Nov-2024 13:39    2277
RISCVTargetTransformInfo.cpp                       05-Nov-2024 13:39     76K
RISCVTargetTransformInfo.h                         05-Nov-2024 13:39     16K
RISCVVectorPeephole.cpp                            05-Nov-2024 13:39    9830