Index of /shared/bigslow/tmp/llvm-project/llvm/lib/Target/RISCV/


../
AsmParser/                                         11-Jan-2024 12:35       -
Disassembler/                                      11-Jan-2024 12:35       -
GISel/                                             11-Jan-2024 12:35       -
MCA/                                               11-Jan-2024 12:35       -
MCTargetDesc/                                      11-Jan-2024 12:35       -
TargetInfo/                                        11-Jan-2024 12:35       -
CMakeLists.txt                                     11-Jan-2024 12:35    2751
RISCV.h                                            11-Jan-2024 12:35    3607
RISCV.td                                           11-Jan-2024 12:35    2405
RISCVAsmPrinter.cpp                                11-Jan-2024 12:35     35K
RISCVCallingConv.td                                11-Jan-2024 12:35    1686
RISCVCodeGenPrepare.cpp                            11-Jan-2024 12:35    3894
RISCVCombine.td                                    11-Jan-2024 12:35     940
RISCVDeadRegisterDefinitions.cpp                   11-Jan-2024 12:35    3892
RISCVExpandAtomicPseudoInsts.cpp                   11-Jan-2024 12:35     26K
RISCVExpandPseudoInsts.cpp                         11-Jan-2024 12:35     20K
RISCVFeatures.td                                   11-Jan-2024 12:35     53K
RISCVFoldMasks.cpp                                 11-Jan-2024 12:35    7244
RISCVFrameLowering.cpp                             11-Jan-2024 12:35     60K
RISCVFrameLowering.h                               11-Jan-2024 12:35    3937
RISCVGISel.td                                      11-Jan-2024 12:35    7027
RISCVGatherScatterLowering.cpp                     11-Jan-2024 12:35     19K
RISCVISelDAGToDAG.cpp                              11-Jan-2024 12:35    137K
RISCVISelDAGToDAG.h                                11-Jan-2024 12:35    9113
RISCVISelLowering.cpp                              11-Jan-2024 12:35    782K
RISCVISelLowering.h                                11-Jan-2024 12:35     41K
RISCVInsertReadWriteCSR.cpp                        11-Jan-2024 12:35    3392
RISCVInsertVSETVLI.cpp                             11-Jan-2024 12:35     57K
RISCVInsertWriteVXRM.cpp                           11-Jan-2024 12:35     14K
RISCVInstrFormats.td                               11-Jan-2024 12:35     19K
RISCVInstrFormatsC.td                              11-Jan-2024 12:35     11K
RISCVInstrFormatsV.td                              11-Jan-2024 12:35    8675
RISCVInstrGISel.td                                 11-Jan-2024 12:35     977
RISCVInstrInfo.cpp                                 11-Jan-2024 12:35    117K
RISCVInstrInfo.h                                   11-Jan-2024 12:35     13K
RISCVInstrInfo.td                                  11-Jan-2024 12:35     87K
RISCVInstrInfoA.td                                 11-Jan-2024 12:35     19K
RISCVInstrInfoC.td                                 11-Jan-2024 12:35     40K
RISCVInstrInfoD.td                                 11-Jan-2024 12:35     28K
RISCVInstrInfoF.td                                 11-Jan-2024 12:35     34K
RISCVInstrInfoM.td                                 11-Jan-2024 12:35    5809
RISCVInstrInfoV.td                                 11-Jan-2024 12:35     76K
RISCVInstrInfoVPseudos.td                          11-Jan-2024 12:35    316K
RISCVInstrInfoVSDPatterns.td                       11-Jan-2024 12:35     74K
RISCVInstrInfoVVLPatterns.td                       11-Jan-2024 12:35    157K
RISCVInstrInfoXCV.td                               11-Jan-2024 12:35     30K
RISCVInstrInfoXSf.td                               11-Jan-2024 12:35     27K
RISCVInstrInfoXTHead.td                            11-Jan-2024 12:35     38K
RISCVInstrInfoXVentana.td                          11-Jan-2024 12:35    2039
RISCVInstrInfoZa.td                                11-Jan-2024 12:35    6725
RISCVInstrInfoZb.td                                11-Jan-2024 12:35     38K
RISCVInstrInfoZc.td                                11-Jan-2024 12:35     10K
RISCVInstrInfoZcmop.td                             11-Jan-2024 12:35    1297
RISCVInstrInfoZfa.td                               11-Jan-2024 12:35     11K
RISCVInstrInfoZfbfmin.td                           11-Jan-2024 12:35    3966
RISCVInstrInfoZfh.td                               11-Jan-2024 12:35     30K
RISCVInstrInfoZicbo.td                             11-Jan-2024 12:35    3796
RISCVInstrInfoZicfiss.td                           11-Jan-2024 12:35    3045
RISCVInstrInfoZicond.td                            11-Jan-2024 12:35    2483
RISCVInstrInfoZimop.td                             11-Jan-2024 12:35    2362
RISCVInstrInfoZk.td                                11-Jan-2024 12:35    8793
RISCVInstrInfoZvfbf.td                             11-Jan-2024 12:35    1426
RISCVInstrInfoZvk.td                               11-Jan-2024 12:35     41K
RISCVMachineFunctionInfo.cpp                       11-Jan-2024 12:35    1626
RISCVMachineFunctionInfo.h                         11-Jan-2024 12:35    6194
RISCVMacroFusion.cpp                               11-Jan-2024 12:35    5976
RISCVMacroFusion.h                                 11-Jan-2024 12:35    1001
RISCVMakeCompressible.cpp                          11-Jan-2024 12:35     14K
RISCVMergeBaseOffset.cpp                           11-Jan-2024 12:35     17K
RISCVMoveMerger.cpp                                11-Jan-2024 12:35    8320
RISCVOptWInstrs.cpp                                11-Jan-2024 12:35     22K
RISCVPostRAExpandPseudoInsts.cpp                   11-Jan-2024 12:35    3641
RISCVProcessors.td                                 11-Jan-2024 12:35     15K
RISCVPushPopOptimizer.cpp                          11-Jan-2024 12:35    5232
RISCVRVVInitUndef.cpp                              11-Jan-2024 12:35     10K
RISCVRedundantCopyElimination.cpp                  11-Jan-2024 12:35    5823
RISCVRegisterInfo.cpp                              11-Jan-2024 12:35     31K
RISCVRegisterInfo.h                                11-Jan-2024 12:35    4052
RISCVRegisterInfo.td                               11-Jan-2024 12:35     23K
RISCVSchedRocket.td                                11-Jan-2024 12:35    8817
RISCVSchedSiFive7.td                               11-Jan-2024 12:35     54K
RISCVSchedSyntacoreSCR1.td                         11-Jan-2024 12:35    7148
RISCVSchedule.td                                   11-Jan-2024 12:35     12K
RISCVScheduleV.td                                  11-Jan-2024 12:35     47K
RISCVScheduleZb.td                                 11-Jan-2024 12:35    4654
RISCVSubtarget.cpp                                 11-Jan-2024 12:35    7664
RISCVSubtarget.h                                   11-Jan-2024 12:35    9919
RISCVSystemOperands.td                             11-Jan-2024 12:35     14K
RISCVTargetMachine.cpp                             11-Jan-2024 12:35     22K
RISCVTargetMachine.h                               11-Jan-2024 12:35    2607
RISCVTargetObjectFile.cpp                          11-Jan-2024 12:35    4557
RISCVTargetObjectFile.h                            11-Jan-2024 12:35    1754
RISCVTargetTransformInfo.cpp                       11-Jan-2024 12:35     76K
RISCVTargetTransformInfo.h                         11-Jan-2024 12:35     15K